1. Field of the Invention
The invention relates to stacked circuits, and more particularly to stacked circuits having different crystal orientations.
2. Background Description
SOI (silicon over insulator) technology eliminates bulk CMOS latch-up. SOI technology additionally reduces junction capacitance and allows circuits to operate at higher speeds. Accordingly, SOI technology allows a higher circuit density to be achieved on a silicon wafer.
SOI technology can be applied to many levels of devices. Each level of a multilevel SOI technology based device may be interconnected using vertical plugs which additionally allows metal connections to be used at any level. In a multilevel device, NMOS and PMOS devices may each be restricted to a separate level, or NMOS and PMOS devices may be intermixed on a single level.
For some types of semiconductor devices, it is advantageous to have multiple layers of similar semiconductor material, where each layer has a crystal orientation different from the adjoining layers. However, multi-layer devices are formed with similar semiconductor material having the same crystal orientation from one level to the next. This limitation imposed on the crystal orientation across multiple levels of an integrated circuit results from constraints imposed by the fabrication process.
In particular, semiconductor material is traditionally grown from a pre-existing layer of semiconductor material. During the material growth process, the atoms of the newly formed layer have a strong tendency to orient themselves to the pre-existing substrate's crystal structure as they are laid down. Thus, it becomes very difficult to create a new layer of similar semiconductor material having a crystal orientation which is different from the underlying layer.